Multiple port random access memories are generally configured to include a number of ports, each of which typically represents an independent input/output path for accessing data stored in a memory array. A multiple port RAM may, for example, include a number of read ports and write ports, as well as a scan port for supporting scan-based testing of the memory device. It is noted that the number of read ports need not be the same as the number of write ports.
A significant problem encountered when attempting to increase the number of ports to a programmable memory array concerns the increased complexity of the global wiring management strategy for the memory device. Although it is now possible to design a random access memory with greater than six read ports and six write ports, for example, the total area allocated to support global wiring for all of the read and write ports often exceeds the total device area.
Increasing the memory cell area to accommodate the total number of wiring channels necessitated by global wiring requirements is generally not a desired solution, since such an increase will result in increasing the overall size of the memory array. By way of example, a memory cell of a multiple port random access memory array may require 480 sq. wiring channels to implement the memory cell transistors of a given cell layout. Implementing a conventional global wiring management approach for this cell layout would typically require 600 sq. wiring channels, thus necessitating an increase in memory cell size by approximately 25%.
Another problem encountered when increasing the number of ports for a programmable memory array concerns the node capacitance at the input of the memory cells. In general, the capacitance at the input of a given memory cell increases with each additional write port connected thereto. Such increases in input node capacitance of the memory cell generally results in an appreciable degradation in memory cell write speed.
Yet another problem that arises when attempting to increase the number of ports to a programmable memory array concerns a heightened potential of compromising data integrity or data stability within the memory cell that may occur during a charge sharing event. A write port for a conventional multiple write port RAM, for example, typically includes a pair of series connected transfer gates. Under certain conditions, a charge sharing event may occur in which the cumulative capacitance at the memory cell input and at a node defined between the two transfer gates may contribute to an inadvertent and potentially catastrophic flipping of the memory cell state.
There is, therefore, a need for an improved global wiring management approach for a multiple port random access memory. There exists a further need for an improved global wiring management approach which utilizes a device area-limited design rather than a wiring-limited design. There exists a further need for improved write port circuitry for multiple write port RAM applications which provides for reduced circuit capacitance and memory cell input capacitance, good performance and noise characteristics, and one that does not result in an increase in circuit element size or number of transistors. The present invention fulfills these and other needs.